The introduction of the general purpose microprocessor on a single integrated circuit (IC) into the marketplace resulted in the birth and development of inexpensive computers. These microprocessors included Zilog's Z80, and Intel's 8088. During the early development phase, different designs emerged with incompatible system architectures and operating systems. Apple Computer entered the market with the Apple One, and was followed by a number of other manufacturers such as Vector Graphics and Seattle Computer who introduced their own unique computers, using operating systems CP/M and DOS (the parent operating system of MS/DOS) respectively.
When International Business Machines (IBM) introduced the IBM Personal Computer (PC), based on Intel's 8088 and made its peripheral interface bus (IBM PC Bus) and Read Only Memory (ROM) Basic Input Output System (BIOS) public, it rapidly became the defacto industry standard. Many peripheral manufacturers began producing computer graphics and disk drive interface printed circuit boards (PCB) compatible with the IBM PC Bus. The next step of this evolution produced the IBM PC AT based on the 16-bit Intel 80286, which resulted in the expansion of the 8-bit based IBM PC Bus into a 16-bit peripheral interface bus for the IBM PC AT called the IBM AT ISA Bus. This path eventually lead to the 32-bit world of the 80386 and the 80486, with the ISA Bus remaining the defacto standard interface for peripheral devices. Meanwhile, peripheral device performance and microprocessor speeds continued their rapid increase and as a result, the ISA Bus is now a bottleneck and a serious impediment to improved performance of the PC as a whole.
The early Winchester hard disk drives developed for PCs had data burst rates of about 0.5 Mbits/sec and mean seek time of 100 msecs, which the ISA bus was able to service fairly efficiently. However, after over a decade of rapid development, hard disk drives are now capable of data burst rates of over 10 MBytes/sec and mean seek times of under 12 msecs. Increasingly, "intelligent" circuitry was added to the hard drives and another defacto peripheral interface standard soon gained wide acceptance. This standard is known as the Integrated Device Electronics interface bus (IDE Bus) and is the interface between a hard disk drive and a simplified conventional hard disk controller card. The disk controller card is in turn coupled to the computer via the ISA Bus. Eventually, the IDE Bus became the ANSIS-ATA standard proposal currently evolving but adopted by most manufacturers. The IDE interface is a 40-pin flat cable format and is capable of supporting data burst rates possibly exceeding 20 MByte/sec. In contrast, the conventional ISA interface can theoretically support burst rates of 5 MByte/sec on the programmed I/O cycles generally used for disk drive operations but in practice a typical ISA IDE disk drive only achieves an average data transfer rate of less than 1 MByte/sec typically.
FIG. 1 shows a block diagram of the conventional IDE hard disk interface between the Central Processing Unit (CPU) 1 of the computer and a pair of hard drives 10 & 11.
The hard drives 10 and 11 ("disk drive" is used herein interchangeably with "hard drive") illustrated in FIG. 1 are ATA (Advanced Technology Attached) hard disk drives. The ATA standard interface having 40 total lines, includes a three-bit address bus designated as DA0, DA1, and DA2 used for indexing drive registers; a 16 bit bidirectional data bus designated as DD0 through DD15; a data width format signal designated as IOCS16- indicating either an 8 or 16 data bit capability, a write strobe signal designated as DIOW-; a read strobe signal designated as DIOR-; an interrupt request signal INTRQ, a status signal I/O Channel Ready designated as IORDY, and host chip select 0 and 1 signal lines respectively designed as CS1FX- and CS3FX-. The two host chip select signal lines CS1FX- and CS3FX- which act similar to an address line, select access of either Command Block registers or Control Block registers within an attached ATA disk drive. Other signals present within the ATA standard interface that may be significant to the description of the present invention will be described below.
The disk drives 10 and 11 may be designated disk drive 0 and disk drive 1 by the ATA cable connection for the ATA standard interface signal CSEL (ground=drive 0, open=drive 1) or by setup switches or jumper wires within the disk drive electronics that are read upon reset. Only one of the disk drives 10 or 11 connected to the same ATA cable 110 can be accessed at any one time. The selection of whether disk drive 0 or disk drive 1 is to be accessed is controlled through use of the drive/head register which is embedded in each disk drive. Both disk drives 10 and 11 simultaneously respond to writes on the cable to the drive/head register, however only the selected drive will respond to writes to other registers therein. Bit 4 of each drive/head register, designated DRV, is used to select the drive that should be active to receive the other drive register accesses and is compared by the drive with its CSEL or switch/jumper configuration as drive 0 or drive 1. If the host CPU 1 sets DRV to zero, then drive 0 is selected and further register accesses are to drive 0 registers. If the host CPU 1 sets DRV to one, then drive 1 is selected and further register accesses are to drive 1 registers.
Accesses to the disk drives occur during cycles such as those illustrated in FIG. 1A as either ATA read cycles 190 or ATA write cycles 191. Note that during all ATA read or write cycles either a DACK-, CS1FX-, or CS3FX- signal becomes active as illustrated by the CS1FX-/CS3FX- waveform 181. Activation of DACK-, CS1FX-, or CS3FX- is then followed by either DIOR- active low signal or DIOW- active low signal as represented by the DIOR- waveform 182 or the DIOW- waveform 183. If neither DACK-, CS1FX-, nor CS3FX- is active, then no write or read operation is being performed to the disk drives regardless of the condition of other signals on the ATA cable 110 including DIOR- and DIOW- as illustrated by the ATA NOOP cycles 192 and 193.
If a read or write host CPU transfer cycle to or from the ATA drive needs to be extended, then the ATA drive deasserts the IORDY signal inactive low. This indicates that the selected hard disk drive needs further time to complete the present operation before any other operation may take place. Otherwise IORDY is pulled up to an active one or an active high level by a pullup resistor.
Various I.C. manufacturers such as Chips & Technologies and Opti Incorporated produce versions of a PC chip set 2 to convert non-standard CPU signals into ISA Bus signals. Additionally, an ISA Interface 5 provides a second level of minor protocol conversion between the ISA Bus and the IDE Bus interface to the hard disks 10 & 11. The ISA Interface 5 includes a register such as an LS244 which provides system compatibility with a floppy drive (not shown).
However, because of the data transfer speed limitations imposed by the ISA Bus standard, of 8 MHz, there is very little incentive to produce hard drives with higher data transfer rates. As a result, most of recent improvements to the hard drive technology have been concentrated in the area of physical size reduction and increased data capacity. Therefore the introduction of a new high performance peripheral interface standard will enable the faster CPU of the computer or microprocessor in the computer to take advantage of faster hard drives already available today and further create an incentive for hard drive manufacturers to increase data transfer rates.
Meanwhile, in the field of computer graphics, a very similar evolution was taking place. Early PC monochrome graphics cards based on the monochrome display adapter (MDA) had no graphics capabilities and could only display text. This was followed by the Color Graphics Adapter (CGA) with 4 color graphics capability. In contrast, today's Enhanced Graphics Adapter (EGA), Video Graphics Array (VGA) and the Super VGA (SVGA) are capable of both text and higher resolution graphics. As a result, a new class of multifrequency displays were introduced, starting at EGA resolution (640*350) and going up to 640*400, 640*480, 800*600, 1024*768, or even higher. In addition to the higher resolution, multifrequency displays also offer more colors. When operated in a digital mode, they have 64 color capability.
FIG. 2 shows a block diagram of a conventional interface between the CPU 1 and the graphics display device 20. The PC chip set 2 provides an interface between the CPU bus and the ISA bus. Additionally, a VGA Interface Controller 6 provides a second level of protocol conversion between the ISA Bus and the VGA Bus interface to the graphics display device 20.
The two techniques commonly used for storing color information are the packed pixel method and the color plane method as illustrated in FIGS. 3A and 3B respectively. A pixel is a dot having an X-Y position defined on the graphics display. Both VGA and SVGA define color plane oriented devices and also support emulation modes that use packed pixels. With packed pixels, all the color information for a pixel is packed into one word of memory data. With the color plane approach, the display memory is separated into several independent planes of memory, with each plane dedicated to controlling one color component (such as the primary colors red, green or blue). Each pixel occupies one bit position in each color plane. The color plane method makes more efficient use of the display memory. Nevertheless, in both the packed pixel and the color plane methods, a large amount of display memory space is needed to support color graphics applications, and there exists a potential for a high volume of pixel data read/write requests by the CPU to the display memory.
This is because the VGA and many SVGA implementations, like its predecessors, are non-intelligent display device standards; i.e. they have no on-board drawing or processing capability. The CPU is responsible for computing any changes required in the display and drawing directly into display memory in real-time. Hence there is potentially a very high volume of data that must be read from or written by the CPU to and from the display memory, all of which must pass through the peripheral interface between the CPU and the display memory. Therefore it is increasingly clear that the ISA bus is inadequate for today's real-time computer graphics applications requiring high speed and high volume transfer of data, such as three dimensional simulation of a number of mechanical moving parts in real-time or the animation used in the movie industry.
Hence there is an urgent need for a new high performance peripheral interface capable of keeping up with the demands of today's 32-bit microprocessors running at typical speeds of 50 MHz and accessing high performance peripherals such as high speed hard drives and high resolution graphics displays.
A consortium of video equipment manufacturers has collectively agreed to support a new standard for the CPU local bus which is substantially faster than the IBM AT ISA Bus.
This new standard has been named the Video Electronic Standard Association (VESA) VL-Bus. Another CPU local bus standard currently gaining acceptance is the Peripheral Component Interface Local (PCI) bus standard. Both the VL bus and the PCI bus do not directly support DMA data transfers with disk drives or other peripheral devices attached to the IDE bus. However, some current disk drives transfer data through DMA transfers faster than through PIO transfers. Thus, one shortcoming of the VL and PCI buses is that they cannot exploit the faster data transfer bandwidth that some disk drives have in the DMA mode.
In some applications, the host side PIO data bandwidth is slower than the IDE side data bandwidth. This condition may arise because the newer disk drives are more efficient than the CPU in transferring data, or because the CPU is operated at a slower speed to conserve energy. Accordingly, in these applications, it is desirable to transfer data from the peripheral bus to a peripheral interface device that interfaces a host bus with peripheral devices at a clock rate faster than the CPU energy saving clock rate so that the data is available in the peripheral interface device when the CPU clock rate is returned to normal.